The present invention relates to an arrangement for testing printed-circuit boards having an electric connection panel linked to an evaluator arrangement and having an adaptor device, which, on the one hand, can be connected to the printed-circuit board to be tested and, on the other hand, is linked to the electric connection panel, whereby the adaptor device consists of several printed circuit-boards lying side- by-side and at a right angle to the surface of the printed-circuit board to be tested, which are connected over circuit-board conductors to contact elements on the printed-circuit boards, turned toward the connection panel.
In a known arrangement of this type (EP 0 142 119 B1), the adaptor device contains two sets of printed-circuit boards lying side-by-side, which each have contacts on their narrow input-side, which are arranged in intervals corresponding to half of the standard contact spacing of 2.54 mm. These contacts are connected over circuit-board conductors on the printed circuit-boards to contact elements, which lie on a narrow output side of the printed circuit boards, opposite the narrow input-side. These contact elements are arranged on the narrow output-side in intervals, which correspond to the standard contact spacing. By placing the two sets of printed circuit-boards, designed according to the described method, one over another in a cross-wise arrangement, test points on the printed-circuit board to be tested, arranged in half of the standard contact spacing, can be connected with contact surfaces on a basic grid, whereby the contact surfaces are distributed in the standard contact spacing arrangement. In this way, an evaluator arrangement connected through an electric connection panel cannot only test printed-circuit boards with test points in standard contact spacing, but can also test printed-circuit boards with test points in half of this contact spacing. In the case of the known arrangement, the electric connection panel, which connects the contact surfaces on the basic grid with the evaluator arrangement, is located below the basic grid.